Image credit: Western Digital
At the RISC-V Summit, Western Digital (WD) announced three open-source innovations related to the RISC-V instruction set architecture (ISA): a new open source RISC-V CPU core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator.
WD Developed Its Own RISC-V CPU Core
WD announced that it has built its own RISC-V core, which it calls “SweRV,” and that it intends to open source it. The CPU core features a two-way superscalar design, 32-bit in-order architecture, and nine stage pipeline.
The company claims performance of 4.9 CoreMarks/MHz, a clock speed of up to 1.8GHz on a 28nm CMOS process technology. WD will initially use the processor in its flash controllers and SSDs. WD expects the open sourcing of the core to “drive development of new data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more.”
Other RISC-V Innovations
WD also announced the “OmniXtend,” which is a new open approach to providing cache coherent memory over an Ethernet fabric, according to the company. It’s a memory-centric system architecture that provides open standard interfaces for access and data sharing across different types of processors, including CPUs, GPUs, machine learning accelerators, FPGAs, and others. The OmniXtend solution also offers support for future advanced fabrics that connect compute, storage, memory, and I/O components.
Finally, the company announced its open sourceSweRV Instruction Set Simulator (ISS), a program that simulates the execution of instructions on the SweRV processor. WD itself used the ISS to validate the design of the SweRV core with more than 10 billion instructions executed. WD expects the SweRV core and its corresponding simulator will advance the adoption of the open source RISC-V ISA.
Western Digital Bets on RISC-V ISA
Western Digital is one of the founding members of the RISC-V Foundation, which was created back in 2015. The foundation also includes companies such as AMD, Google, IBM, Nvidia, NXP, and Qualcomm.
Last year, WD committed to shipping over one billion RISC-V cores in its storage devices, per year. Eventually, the company aims to replace all the microcontrollers in its products with RISC-V cores, which should double the number of shipped RISC-V cores to over two billion a year.